module reg_file_top_tb ();
  
  reg clk,rst,RegW;
  reg [4:0] ra1,ra2,wa;
  
  reg [7:0] wd;
  
  wire [7:0] rd1,rd2;

 reg_file_top U1(clk,rst,RegW,ra1,ra2,wa,wd,rd1,rd2);

  // initial #200 $finish;
    initial begin
    clk=0;  
    rst=0; 
    forever #10 clk=~clk; 
    end 
    
    initial begin    
    RegW=1; wd=8'b11111110; wa=5'b00000; #20;
    
    RegW=1; wd=8'b11111100; wa=5'b00001; #20;
   
    RegW=1; wd=8'b11111000; wa=5'b00010; #20;
   
    RegW=0; ra1=5'b00000; ra2=5'b00001; #20;
   
    RegW=0; ra1=5'b00001; ra2=5'b00010; #20;

    $stop;
  end

  endmodule